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PatchworkOS
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Go to the source code of this file.
Data Structures | |
| struct | pml_entry_t |
| struct | pml_t |
| A page table level. More... | |
| struct | page_table_t |
| A page table structure. More... | |
Macros | |
| #define | PML_PIN_DEPTH_MAX 3 |
| Maximum pin depth for a page. | |
| #define | PML_ADDR_OFFSET_BITS 12 |
| Number of bits used for the offset within a page. | |
| #define | PML_ADDR_MASK 0x000FFFFFFFFFF000ULL |
| Mask for the address in a page table entry. | |
| #define | PML_FLAGS_MASK |
| Mask for all pml flags. | |
| #define | PML_INDEX_BITS 9 |
| Number of bits used to index into a page table level. | |
| #define | PML_INDEX_TO_ADDR_NO_WRAP(index, level) ((uintptr_t)(index) << (((level) - 1) * PML_INDEX_BITS + PML_ADDR_OFFSET_BITS)) |
| Calculates the lowest virtual address that maps to a given index at a specified page table level, without wrapping. | |
| #define | PML_VIRT_ADDR_BITS (PML_INDEX_BITS * PML_LEVEL_AMOUNT + PML_ADDR_OFFSET_BITS) |
| Total number of bits used for virtual addresses. | |
| #define | PML_LOWER_HALF_START (0) |
| The start of the lower half of the address space. | |
| #define | PML_LOWER_HALF_END ((1ULL << (PML_VIRT_ADDR_BITS - 1)) - PAGE_SIZE) |
| The end of the lower half of the address space. | |
| #define | PML_HIGHER_HALF_START (~((1ULL << (PML_VIRT_ADDR_BITS - 1)) - 1)) |
| The start of the higher half of the address space. | |
| #define | PML_HIGHER_HALF_END (~0ULL & ~(PAGE_SIZE - 1)) |
| The end of the higher half of the address space. | |
| #define | PML_HIGHER_TO_LOWER(addr) ((uintptr_t)(addr) - PML_HIGHER_HALF_START) |
| Converts an address from the higher half to the lower half. | |
| #define | PML_LOWER_TO_HIGHER(addr) ((uintptr_t)(addr) + PML_HIGHER_HALF_START) |
| Converts an address from the lower half to the higher half. | |
| #define | PML_ENSURE_LOWER_HALF(addr) ((uintptr_t)(addr) >= PML_HIGHER_HALF_START ? PML_HIGHER_TO_LOWER(addr) : (uintptr_t)(addr)) |
| Ensures that the given address is in the lower half of the address space. | |
| #define | PML_ADDR_TO_INDEX(addr, level) |
| Calculates the index into a page table level for a given virtual address. | |
| #define | PML_INDEX_TO_ADDR(index, level) |
| Calculates the lowest virtual address that maps to a given index at a specified page table level. | |
| #define | PML2_SIZE (1ULL << (PML_INDEX_BITS + PML_ADDR_OFFSET_BITS)) |
| Size of the region mapped by a single PML2 entry. | |
| #define | PML3_SIZE (1ULL << (2 * PML_INDEX_BITS + PML_ADDR_OFFSET_BITS)) |
| Size of the region mapped by a single PML3 entry. | |
| #define | PML4_SIZE (1ULL << (3 * PML_INDEX_BITS + PML_ADDR_OFFSET_BITS)) |
| Size of the region mapped by a single PML4 entry. | |
| #define | PML_MAX_CALLBACK ((1 << 8) - 1) |
| Maximum number of callbacks that can be registered for a page table. | |
| #define | PML_CALLBACK_NONE ((1 << 8) - 1) |
| Special callback ID that indicates no callback is associated with the page. | |
| #define | PML_PAGE_BUFFER_SIZE 64 |
| Size of the page buffer used to batch page allocations and frees. | |
Typedefs | |
| typedef uint8_t | pml_callback_id_t |
| Callback ID type. | |
| typedef uint64_t(* | pml_alloc_pages_t) (void **, uint64_t) |
| Generic page allocation function type. | |
| typedef void(* | pml_free_pages_t) (void **, uint64_t) |
| Generic page free function type. | |
Enumerations | |
| enum | pml_flags_t { PML_NONE = 0 , PML_PRESENT = (1ULL << 0) , PML_WRITE = (1ULL << 1) , PML_USER = (1ULL << 2) , PML_WRITE_THROUGH = (1ULL << 3) , PML_CACHE_DISABLED = (1ULL << 4) , PML_ACCESSED = (1ULL << 5) , PML_DIRTY = (1ULL << 6) , PML_SIZE = (1ULL << 7) , PML_GLOBAL = (1ULL << 8) , PML_OWNED = (1ULL << 9) , PML_NO_EXECUTE = (1ULL << 63) } |
| enum | pml_level_t { PML1 = 1 , PT = 1 , PML2 = 2 , PD = 2 , PML3 = 3 , PDPT = 3 , PML4 = 4 , PML_LEVEL_AMOUNT = 4 } |
| Enums for the different page table levels. More... | |
| enum | pml_index_t { PML_INDEX_LOWER_HALF_MIN = 0 , PML_INDEX_LOWER_HALF_MAX = 255 , PML_INDEX_HIGHER_HALF_MIN = 256 , PML_INDEX_HIGHER_HALF_MAX = 511 , PML_INDEX_AMOUNT = 512 } |
| Indexes into a pml level. More... | |