apic.h

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#pragma once
 
#include <kernel/acpi/tables.h>
#include <kernel/cpu/interrupt.h>
#include <kernel/defs.h>
 
#include <stdint.h>
 
typedef struct cpu cpu_t;
 
typedef uint8_t lapic_id_t;
 
typedef uint32_t ioapic_gsi_t;
 
typedef enum
{
    APIC_TIMER_MASKED = 0x10000, 
    APIC_TIMER_PERIODIC = 0x20000,
    APIC_TIMER_ONE_SHOT = 0x00000
} apic_timer_mode_t;
 
typedef enum
{
    APIC_TIMER_DIV_16 = 0x3,
    APIC_TIMER_DIV_32 = 0x4,
    APIC_TIMER_DIV_64 = 0x5,
    APIC_TIMER_DIV_128 = 0x6,
    APIC_TIMER_DIV_DEFAULT = APIC_TIMER_DIV_16
} apic_timer_divider_t;
 
typedef enum
{
    LAPIC_MSR_ENABLE = 0x800,
    LAPIC_MSR_BSP = 0x100
} lapic_msr_flags_t;
 
typedef enum
{
    LAPIC_REG_ID = 0x020,
    LAPIC_REG_VERSION = 0x030,
    LAPIC_REG_TASK_PRIORITY = 0x080,
    LAPIC_REG_ARBITRATION_PRIORITY = 0x090,
    LAPIC_REG_PROCESSOR_PRIORITY = 0x0A0,
    LAPIC_REG_EOI = 0x0B0,
    LAPIC_REG_REMOTE_READ = 0x0C0,
    LAPIC_REG_LOGICAL_DEST = 0x0D0,
    LAPIC_REG_DEST_FORMAT = 0x0E0,
    LAPIC_REG_SPURIOUS = 0x0F0,
    LAPIC_REG_ISR_BASE = 0x100,
    LAPIC_REG_TMR_BASE = 0x180,
    LAPIC_REG_IRR_BASE = 0x200,
    LAPIC_REG_ERROR_STATUS = 0x280,
    LAPIC_REG_LVT_CMCI = 0x2F0,
    LAPIC_REG_ICR0 = 0x300,
    LAPIC_REG_ICR1 = 0x310,
    LAPIC_REG_LVT_TIMER = 0x320,
    LAPIC_REG_LVT_THERMAL = 0x330,
    LAPIC_REG_LVT_PERFCTR = 0x340,
    LAPIC_REG_LVT_LINT0 = 0x350,
    LAPIC_REG_LVT_LINT1 = 0x360,
    LAPIC_REG_LVT_ERROR = 0x370,
    LAPIC_REG_TIMER_INITIAL_COUNT = 0x380,
    LAPIC_REG_TIMER_CURRENT_COUNT = 0x390,
    LAPIC_REG_TIMER_DIVIDER = 0x3E0
} lapic_register_t;
 
#define LAPIC_REG_ICR1_ID_OFFSET 24
 
typedef enum
{
    LAPIC_SPURIOUS_ENABLE = (1 << 8),
    LAPIC_LVT_MASKED = (1 << 16)
} lapic_flags_t;
 
typedef enum
{
    LAPIC_ICR_FIXED = (0 << 8),
    LAPIC_ICR_LOWEST_PRIORITY = (1 << 8),
    LAPIC_ICR_SMI = (2 << 8),
    LAPIC_ICR_NMI = (4 << 8),
    LAPIC_ICR_INIT = (5 << 8),
    LAPIC_ICR_STARTUP = (6 << 8)
} lapic_icr_delivery_mode_t;
 
typedef enum
{
    LAPIC_ICR_CLEAR_INIT_LEVEL = (1 << 14)
} lapic_icr_flags_t;
 
typedef enum
{
    IOAPIC_MMIO_REG_SELECT = 0x00,
    IOAPIC_MMIO_REG_DATA = 0x10
} ioapic_mmio_register_t;
 
typedef enum
{
    IOAPIC_REG_VERSION = 0x01
} ioapic_register_t;
 
#define IOAPIC_REG_REDIRECTION(pin, high) (0x10 + (pin) * 2 + (high))
 
#define APIC_TIMER_TICKS_FIXED_POINT_OFFSET 32
 
typedef struct PACKED
{
    union {
        uint32_t raw;
        struct PACKED
        {
            uint8_t version;
            uint8_t reserved;
            uint8_t maxRedirs;
            uint8_t reserved2;
        };
    };
} ioapic_version_t;
 
typedef enum
{
    IOAPIC_DELIVERY_NORMAL = 0,
    IOAPIC_DELIVERY_LOW_PRIO = 1,
    IOAPIC_DELIVERY_SMI = 2,
    IOAPIC_DELIVERY_NMI = 4,
    IOAPIC_DELIVERY_INIT = 5,
    IOAPIC_DELIVERY_EXTERNAL = 7
} ioapic_delivery_mode_t;
 
typedef enum
{
    IOAPIC_DESTINATION_PHYSICAL = 0,
    IOAPIC_DESTINATION_LOGICAL = 1
} ioapic_destination_mode_t;
 
typedef enum
{
    IOAPIC_TRIGGER_EDGE = 0,
    IOAPIC_TRIGGER_LEVEL = 1
} ioapic_trigger_mode_t;
 
typedef enum
{
    IOAPIC_POLARITY_HIGH = 0,
    IOAPIC_POLARITY_LOW = 1
} ioapic_polarity_t;
 
typedef union {
    struct PACKED
    {
        uint8_t vector;
        uint8_t deliveryMode : 3;
        uint8_t destinationMode : 1;
        uint8_t deliveryStatus : 1;
        uint8_t polarity : 1;
        uint8_t remoteIRR : 1;
        uint8_t triggerMode : 1;
        uint8_t mask : 1;
        uint64_t reserved : 39;
        uint8_t destination : 8;
    };
    struct PACKED
    {
        uint32_t low;
        uint32_t high;
    } raw;
} ioapic_redirect_entry_t;
 
void apic_timer_one_shot(interrupt_t vector, uint32_t ticks);
 
uint64_t apic_timer_ticks_per_ns(void);
 
void lapic_cpu_init(void);
 
lapic_id_t lapic_self_id(void);
 
void lapic_write(lapic_register_t reg, uint32_t value);
 
uint32_t lapic_read(lapic_register_t reg);
 
void lapic_send_init(lapic_id_t id);
 
void lapic_send_sipi(lapic_id_t id, void* entryPoint);
 
void lapic_send_ipi(lapic_id_t id, interrupt_t vector);
 
void lapic_eoi(void);
 
uint32_t ioapic_read(ioapic_t* ioapic, ioapic_register_t reg);
 
void ioapic_write(ioapic_t* ioapic, ioapic_register_t reg, uint32_t value);
 
ioapic_version_t ioapic_get_version(ioapic_t* ioapic);
 
ioapic_t* ioapic_from_gsi(ioapic_gsi_t gsi);
 
void ioapic_set_redirect(interrupt_t vector, ioapic_gsi_t gsi, ioapic_delivery_mode_t deliveryMode,
    ioapic_polarity_t polarity, ioapic_trigger_mode_t triggerMode, cpu_t* cpu, bool enable);