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| #define | LAPIC_REG_ID_OFFSET 24 |
| | The offset at which the lapic id is stored in the LAPIC_REG_ID register.
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| enum | lapic_msr_flags_t { LAPIC_MSR_ENABLE = 0x800
, LAPIC_MSR_BSP = 0x100
} |
| | Local APIC MSR Flags. More...
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| enum | lapic_register_t {
LAPIC_REG_ID = 0x020
, LAPIC_REG_VERSION = 0x030
, LAPIC_REG_TASK_PRIORITY = 0x080
, LAPIC_REG_ARBITRATION_PRIORITY = 0x090
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LAPIC_REG_PROCESSOR_PRIORITY = 0x0A0
, LAPIC_REG_EOI = 0x0B0
, LAPIC_REG_REMOTE_READ = 0x0C0
, LAPIC_REG_LOGICAL_DEST = 0x0D0
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LAPIC_REG_DEST_FORMAT = 0x0E0
, LAPIC_REG_SPURIOUS = 0x0F0
, LAPIC_REG_ISR_BASE = 0x100
, LAPIC_REG_TMR_BASE = 0x180
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LAPIC_REG_IRR_BASE = 0x200
, LAPIC_REG_ERROR_STATUS = 0x280
, LAPIC_REG_LVT_CMCI = 0x2F0
, LAPIC_REG_ICR0 = 0x300
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LAPIC_REG_ICR1 = 0x310
, LAPIC_REG_LVT_TIMER = 0x320
, LAPIC_REG_LVT_THERMAL = 0x330
, LAPIC_REG_LVT_PERFCTR = 0x340
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LAPIC_REG_LVT_LINT0 = 0x350
, LAPIC_REG_LVT_LINT1 = 0x360
, LAPIC_REG_LVT_ERROR = 0x370
, LAPIC_REG_TIMER_INITIAL_COUNT = 0x380
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LAPIC_REG_TIMER_CURRENT_COUNT = 0x390
, LAPIC_REG_TIMER_DIVIDER = 0x3E0
} |
| | Local APIC Registers. More...
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| enum | lapic_flags_t { LAPIC_SPURIOUS_ENABLE = (1 << 8)
, LAPIC_LVT_MASKED = (1 << 16)
} |
| | Local APIC Flags. More...
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| enum | lapic_icr_delivery_mode_t {
LAPIC_ICR_FIXED = (0 << 8)
, LAPIC_ICR_LOWEST_PRIORITY = (1 << 8)
, LAPIC_ICR_SMI = (2 << 8)
, LAPIC_ICR_NMI = (4 << 8)
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LAPIC_ICR_INIT = (5 << 8)
, LAPIC_ICR_STARTUP = (6 << 8)
} |
| | Local APIC ICR Delivery Modes. More...
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| enum | lapic_icr_flags_t { LAPIC_ICR_CLEAR_INIT_LEVEL = (1 << 14)
} |
| | Local APIC ICR Flags. More...
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